A 3.3V 8Mb embedded DRAM achieves a 1.6GB/s data transfer rate and page-fault tolerance. Accessing across different pages is performed in a minimum column cycle using a data latch between sense amplifier and global data-line-select gate. High bandwidth is achieved with a 128b data bus operating at 100MHz. The 113mm2 DRAM macro is embedded in a sea of gates in 0.5mm CMOS two-layer metal technology.

18.2 A 10Mb 3D Frame-Buffer Memory

The z-compare and a-blend units move the rendering functions on-chip. On-chip ALU, 100MHz triple-ported SRAM cache, and 256b bus from SRAM to DRAM permit 400MB/s rendering speed. A 3.78mm2 cell and 9.94x14.18mm2 chip are achieved using 0.5mm CMOS technology.

18.3 A 295 MHz CMOS 1Mb (x256) Embedded SRAM

A 295MHz 4kword x 256b embedded SRAM in a 0.35mm CMOS 4-layer-metal process technology uses read/write shared sense amps acting as combined sense amps, write circuits, and data input level shifters to reduce chip size. Self-timed word-line drivers reduce power consumption. The cycle time is 3.4ns and access time is 3.9ns.

18.4 A 1ns, 1W, 2.5V, 32kb NTL-CMOS SRAM Macro

A 2.5V, 32kb NTL-CMOS SRAM fabricated using 0.4mm BiCMOS technology achieves 1ns access time and 1W power consumption. Techniques to minimize performance variation with process and temperature _include a 6T cell with p-channel access transistors, an NTL address decoder, and a bitline voltage controller.

18.5 A 300MHz 4Mb Wave-Pipeline CMOS SRAM

A 4Mb (64kx64) synchronous wave-pipeline CMOS SRAM is fabricated in 0.25mm CMOS technology. Multi-phase active pulse control (MPAC) enables fully-random 300MHz operation at 2.5V for 2.4GB/s bandwidth. The pulse is generated by a multi-phase PLL (MPPLL) using an array oscillator with 7.5mA consumption. The die is 8x14.1mm2 with a 8.19mm2 cell.

Conclusion (3:30)

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