VIDEO Signal Processing

Chair: T. Meng, Stanford University, Palo Alto, CA
Associate Chair: M. Yoshimoto, Mitsubishi Electric, Hyogo, Japan

17.1 An MPEG-1 Audio/Video Decoder with
Run-Length-Compressed Antialiased Video Overlays (8:30)
D. Galbi, E. Bird, S. Bose, E. Chai, Y.-N. Chang, P. Dermy,
N. Fernando, J.-G. Fritsch, E. Hamilton, B. Hu, E. Hua, F. Liao,
M. Lin, M. Ma, E. Paluch, S. Purcell, H. Yanagi, S. Yang
C-Cube Microsystems, Milpitas, CA

An MPEG-1 video/audio decoder decodes an MPEG-1 stream, 2 layer-1 channels or 2 MPEG-1 audio, SIF-resolution MPEG-1 video, and compressed CCIR 601-resolution antialiased video overlay. The 40MHz, 790k-transistor chip is 132mm2 in 0.5mm CMOS, operates at 2.7-3.6V, and uses 600mW at 3.3V.


17.2 A Half-Pel Precision MPEG-2 Motion-Estimation Processor with Concurrent Three-Vector Search (9:00)

K. Ishihara, S. Masuda, M. Takano, S. Takeuchi, S. Hattori,
H. Nishikawa, T. Yamada, H. Amishiro, M. Yoshimoto

Mitsubishi Electric Engineering Co., Ltd., Hyogo, Japan
The MPEG2 half-pel precision motion-estimation processor supports frame, field, and dual-prime prediction by estimating three vectors concurrently. It integrates 850k transistors in a 13.85x13.55mm2 die in 0.5mm CMOS. At 40MHz for NTSC, peak computation rate is 20GOPS and dissipation is 1.9W.


17.3 A 1.2mW Video-Rate 2D Color Subband Decoder (9:30) B. Gordon, T. Meng, N. Chaddha

Stanford University, Stanford, CA

A two-dimensional subband decoder dissipates <1.2mW for real-time video decompression with 1V supply. The chip reconstructs 4 levels of hierarchical subband structures at 1.3 MPixels/s for color video of 176x240 pixels at 30Frames/s without off-chip memory support. It contains 415k transistors in 0.8mm CMOS.


17.4 A Single-Chip Videophone Video Encoder/Decoder (10:00)

M. Harrand, M. Henry, P. Chaisemartin, P. Mougeat, Y. Durand,
A. Tournier, R. Wilson, J.-C. Herluison, J.-L. Bauer, M. Runtz,
J. Bulone
SGS-Thomson Microelectronics, Crolles Cedex, France

A single-chip video CODEC simultaneously encodes and decodes15QCIF pictures/s in H261 . It realizes a videophone terminal with 4 components. The chip contains 573k transistors with 156mm2 die in 0.7mm CMOS.


Break (10:30)


17.5 A CMOS Continuous-Time NTSC-to-Color-Difference Decoder

J. Parker, W. Current, S. Lewis (10:45)
University of California, Davis, CA

This NTSC decoder includes chrominance IF filter, AGC, timing recovery, demodulators, and hue and saturation controls in 9mm2 and consumes 45mW with 2.5V and -2.5V supplies. For standard NTSC 1Vpp color-bar input, R-Y and B-Y outputs maximum phase and gain errors are 1.1° and 1.5%, respectively.


17.6 A Fully-Integrated Continuous-Time Programmable

CCIR 601 Video Filter (11:15)
I. Bezzam, C. Vinn, R. Rao*
Raytheon Semiconductor, Mountain View, CA
*San Jose State University, San Jose, CA

Current-mode signal-processing is applied to integration of high-order anti-aliasing filters for digitizing video signals. An eighth-order filter is programmable from 1MHz to 10MHz, has +0.25dB and -0.25dB passband gain ripple and handles 2Vpp signals at less than 1% distortion at 5V, dissipating 35mW.


Conclusion (11:45)

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