An 8b bipolar serial-ripple architecture ADC uses a master/slave track-and-hold that drives serially-connected folding amplifiers. A 3.5mm2 prototype in a 1mm 8GHz bipolar process achieves 150MHz conversion rate with 350mW power dissipation at 5V.

16.2 CMOS Folding ADCs with Current-Mode Interpolation (9:00)

Current-mode interpolation and current-steering logic is used for two folding ADCs in 1mm CMOS. An 8b ADC is 4mm2 and requires 250mW and a 6b ADC is 2mm2 and requires 55mW. The maximum sampling rate is 100MHz for low-frequency inputs.

16.3 A 70MSample/s 110mW 8b CMOS Folding Interpolating ADC (9:30)

An 8b ADC using folding and interpolation in 0.8mm CMOS tecnology achieves 70MSample/s with 110mW at 5V, and 45MSample/s with 45mW at 3.3V.

16.4 A 12b 50MSample/s Two-Stage ADC (10:00)

A 12b 50MSample/s two-stage ADC is based on cascaded folding amplifiers. The spurious-free dynamic range is 80dB at Nyquist for 40MSample/s while dissipating 575mW at 5V. The 13.9mm2 die uses a dielectrically-isolated complementary bipolar process.

Break (10:30)

16.5 A 10b 3MSample/s CMOS Cyclic ADC (10:45)

A 10b 3MSample/s CMOS ADC with a microprocessor bus interface is intended for mixed-signal system LSIs such as HDD servo-controllers. The chip is 1.5mm2 in a 0.8mm CMOS technology uses cyclic architecture and consumes 11mW at 2.7V.

16.6 A 2V 10b 20MSample/s Subranging CMOS ADC (11:15)

A 2V 10b 20MSample/s subranging ADC uses voltage-mode for a 5b first-stage ADC and current-mode for a 6b second-stage ADC. The power dissipation is 20mW from 2V. The chip is 12.2mm2 in a dual-threshold 0.5mm CMOS process.

Conclusion (11:45)

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