An 800MHz digital-frequency-synthesizer chip has differential ECL-compatible 12b sine and cosine outputs with -84dBc spectral purity, 0.188Hz tuning resolution, and 12 clock-cycle tuning latency. The 0.8mm triple-level-metal CMOS chip has 94k transistors and 5.9x6.7mm2 core and dissipates 3W at 5V.

15.2 A Fast-Frequency-Switching PLL Synthesizer with a Numerical Phase Comparator (9:00)

A PLL frequency synthesizer using a numerical phase comparator and 20b DAC has 0.65ms switching time for a 16MHz frequency step. All components, except the VCO, are integrated in 5.69x5.51mm2 with 0.6mm BiCMOS, and consume 20mA from 3.3V digital and 4.5V analog supplies.

15.3 A Sine/Cosine Direct-Digital Frequency Synthesizer using an Angle-Rotation Algorithm (9:30)

A direct-digital frequency synthesizer employing an angle-rotation algorithm provides 16b sine and cosine outputs with 100dBc spectral purity and 0.002Hz tuning resolution at 100MHz clock frequency. The 1.2mm CMOS chip contains 58k transistors with 12mm2 core, and dissipates 1.4W at 5V.

15.4 A 2GHz, 6mW BiCMOS Frequency Synthesizer (10:30)

A 2GHz 128-channel frequency synthesizer includes a 3mW VCO, a 2.2mW 16/17 dual-modulus prescaler, a 9b program counter, and a 7b pulse-swallowing counter. The chip in 1mm 20GHz BiCMOS, has 0.28mm2 active area and operates from 3V.

Break (10:30)

15.5 A CMOS 1.8GHz Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler (10:45)

A 1.8GHz VCO using on-chip bondwire inductors demonstrates phase noise of -85dBc/Hz at 10kHz offset from the carrier. The chip in 0.7mm CMOS dissipates 24mW from a 3V supply.

15.6 A 0.18mm CMOS Hot-Standby PLL using a Noise-Immune Adaptive-Gain VCO (11:15)

A 1.0V 200MHz PLL using a hot-standby architecture achieves 92ps peak-to-peak jitter. The 0.18mm two-level-metal CMOS chip contains 2,010 transistors in 0.48x0.45mm2.

Conclusion (11:45)

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