A 16Mb DRAM has 0.9mA self-refresh current using a floating cell plate during the data-retention period to reduce cell leakage. A 20MB RAM disk using this DRAM retains data for 2.5years using a single lithium cell of 190mA-hour capacity. The cell is 1.16x2.62mm2 and the die is 6.5x15. 9mm2 in 0.5mm twin-well triple-poly single-polycide double-metal CMOS.

14.2 A 29ns 64MB DRAM with Hierarchical Array Architecture(9:00)

The experimental 0.25mm CMOS 64Mb DRAM uses a hierarchical word-line scheme and 0.71x1.20mm2 cell. To realize 29ns access time, distributed precharge drivers, shared sense amplifier, overdriven sense amplifier with distributed drivers, and hierarchical I/O lines with semi-direct sensing are used.

14.3 Circuit-Design Techniques for Low-Voltage-Operating And/Or Giga-Scale DRAMs (9:30)

An experimental 1.2V, 16Mb DRAM uses a 0.4mm CMOS process. 49ns access time is achieved by charge-transfer well-sensing. A hierarchical power-line structure reduces subthreshold leakage current in the data-retention mode without deteriorating normal mode operation. The cell is 3.78mm2 and the die is 131.93mm2.

14.4 150MHz 8-Bank 256M Synchronous DRAM with Wave Pipelining

Key circuit techiques _include pulsed logic, wave-pipelining, and a hierarchical I/O architecture. Use of post-charge logic reduces the access time by 10%. The data-path length is divided into 2ns slices to permit 150MHz operation. Burst read cycle time is 6.5ns with a clock access time of 3.5ns. A 0.3mm twin-well CMOS process with a cylindrical stacked-capacitor cell is used to produce a 24.8x14.6mm2 die.

Break (10:30)

14.5 An Experimental 220MHz 1Gb DRAM (10:45)

A 1Gb DRAM employing 0.16mm technology and a 1.5V supply attains a 33ns RAS access time. Eight independently-timed banks and a ringing-cancelling output buffer permit 220MHz synchronous operation. A 714mm2 die area is achieved with a 0.29mm2 memory cell.

14.6 A 1Gb DRAM for File Applications (11:15)

A flexible multi-macro layout, time-shared offset-cancelling sensing, serial charge-recycle refresh, and defective-wordline Hi-Z standby permit 30% die-size reduction with 100% yield improvement over conventional designs. Measured I/O bandwidth is 400MB/s. The cell is 0.54mm2 and the die is 936mm2 using 0.25mm CMOS.

Conclusion (11:45)

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